1. Field of the Invention
The invention relates to a processor and an instruction control method for executing instructions by dynamic pipeline scheduling. More particularly, the invention relates to a processor and an instruction control method for efficiently executing renaming of an update instruction and a read instruction of condition codes which were simultaneously decoded.
2. Description of the Related Arts
Hitherto, in a processor for executing a dynamic pipeline scheduling, processes are executed separately by three units: an instruction issuing unit of in-order depending on program order; an instruction executing unit of out-of-order which does not depend on the program order; and a committing unit of the in-order depending on the program order. That is, the instruction issuing unit fetches a plurality of instructions by the in-order, decodes them, and allows a reservation station to hold the instruction operation (OP code) and an operand. As soon as all operands are prepared in the reservation station and an arithmetic operating unit is made usable, the instruction executing unit speculatively executes the instruction by the out-of-order and obtains a result. The committing unit discriminates a commitment of the instruction on the basis of a branch prediction result or the like, completes the instruction by the in-order, and stores the execution result into a register file or a memory (only in the case of storage). In the processor using such a dynamic pipeline scheduling, in order to keep program order performance of register values, a register update buffer is prepared as a renaming register for holding register update data until completion (commitment) of the instruction. In the processor for simultaneously decoding a plurality of instructions as mentioned above, in renaming in a decoding cycle, it is necessary not only to refer to a renaming map in which renaming histories of up to the previous cycle have been registered but also to rename instructions in consideration of a dependent relation with the instruction before the self instruction among the instructions which were simultaneously decoded. The register renaming is separated into: a renaming map updating process at a decoding stage of the register update instruction serving as a previous instruction; a renaming map referring process at a decoding stage of the register read instruction serving as a following instruction; forward control discrimination at a priority stage of the previous instruction; and a register writing process at an updating stage of the previous instruction. Particularly, when the register update instruction and the register read instruction are simultaneously decoded, it is necessary to rename the register read instruction in consideration of the dependent relation with the register update instruction before the self instruction. Specifically speaking, there is executed forward control such that when the renaming register is update-pending and the value is referred to by the register read instruction from an arithmetic operating unit or the renaming register, an address number of the renaming register and an address number of a source register registered in a reservation station are compared at timing of writing an arithmetic operation result of the previous register update instruction, thereby inputting an execution result of the previous register update instruction into an executing stage of a following register referring instruction and allowing the instruction to be executed.
FIG. 1 is an explanatory diagram of the renaming map updating process in the case where, with respect to the previous register update instruction and the following register read instruction which were simultaneously decoded, a register is allocated onto a register update buffer at the decoding stage of the previous register update instruction. According to such a process, at the decoding stage including the register update instruction and the register read instruction, a dedicated register which holds register update data until an execution result of the instruction is committed is allocated onto the register update buffer (not shown). That is, with respect to four instructions of instruction word registers 218-1 to 218-4, four buffers are allocated onto the register update buffer and information regarding the allocation buffers is held in a renaming map 262. It is now assumed that the register update instruction has been fetched into the instruction word register 218-1 and a next register read instruction has been fetched into the instruction word register 218-2. The renaming map 262 has a pending bit 264 and an allocation address 266. The pending bit 264 is set for each of the allocation registers allocated in correspondence to the four instructions. A relation between a general register REG and an allocation address UBA in the update buffer has been registered as an allocation address 266. Simultaneously with the decoding of the four instructions in the instruction word registers 218-1 to 218-4, for example, as shown with respect to the register update instruction of the instruction word register 218-1, an allocation entry 226-11 corresponding to the instruction is held in a reservation station 226 and an allocation entry 242-11 corresponding to the instruction is held also in a commit stack entry 242. The allocation entry 242-11 in the commit stack entry 242 is constructed by areas of: a valid bit 290; a write register allocation bit 292; a register update buffer allocation bit 294; a write register address 296; an update buffer allocation address 298; an arithmetic operation completion wait bit 300; an instruction operation 302 such as an OP code or the like; a condition code register write bit 304; and condition code data 306. Simultaneously with the allocation corresponding to the instruction of the allocation entry 242-11, bit setting of the write register allocation bit 292, bit setting of the register update buffer allocation bit 294, and writing of the allocation address into the update buffer allocation address 298 are executed in a decoding cycle of the instruction. Subsequent to a first source register area 275 and a second source register area 285, a destination update buffer allocation address 286 and an instruction operation 288 such as an OP code or the like are stored in the allocation entry 226-11 corresponding to the register update instruction held in the reservation station 226. The first source register area 275 is provided with: a first source valid bit 276; a first source register address 278; a first source pending bit 280; a first source register update buffer allocation address (hereinafter, referred to as an “R1 update buffer allocation address”) 282; and a bypass ready bit (forward ready bit) 284. Although areas similar to those in the first source register area 275 are provided for the second source register area 285 as well, they are not shown. In the following explanation and on the drawings, the first source register is expressed as an abbreviation R1 and the second source register is expressed as an abbreviation R2.
FIG. 2 is an explanatory diagram in the case where the following register read instruction which has been fetched in the instruction word register 218-2 and simultaneously decoded refers to the renaming map 262 updated in FIG. 1. Assuming that the instruction in the instruction word register 218-2 is the following register read instruction, the following instruction refers to the renaming map 262 by an address of the register serving as a reading source, for example, by an address “REG0” and refers to the first source register address 278 and the R1 update buffer allocation address 282 in the allocation entry 226-11 of the previous instruction in the reservation station 226 by the pending bit 264 and the allocation address 266. Forward control to a following instruction as shown in FIG. 3 can be made by referring to an execution result of the previous instruction.
According to the forward control to the following instruction in FIG. 3, an R1 update buffer allocation address 314 obtained from the execution result of the previous register update instruction and the R1 update buffer allocation address 282 in the allocation entry 226-11 obtained with reference to the renaming map 262 by the following register read instruction in FIG. 2 are compared, for example, by a matching processing unit 316 at a priority stage of the previous instruction, and if they coincide, the bypass ready bit 284 in the allocation entry 226-11 is set. If a bypass ready to the following instruction, that is, a forward ready is determined from the execution result of the previous instruction as mentioned above, like a process 318, the instruction executing unit is notified of completion of the preparation on the basis of the bypass ready bit 284, the execution result of the previous instruction is forwarded before the commitment, and the following instruction is executed.
In a processor using an SPARC instruction architecture, there is a case where a condition code (hereinbelow, referred to as “CC”) is updated as source data by an update instruction and, thereafter, it is read out by the read instruction and forward control is made. A code indicative of a state of the execution result of a numerical value arithmetic operating instruction such as negative, zero, overflow, or carry is used as such a condition code CC. Also with respect to the instruction for updating the CC register and referring to it as mentioned above, in a processor for simultaneously decoding a plurality of instructions, in the CC renaming in the decoding cycle, it is necessary to not only refer to a CC renaming map in which CC renaming histories of up to the previous cycle have been registered but also perform the CC renaming in consideration of a dependent relation with the instruction before the self instruction in the instructions which were simultaneously decoded. Also, with respect to the instruction which updates the CC register and refers to it, in order to execute the instructions by an out-of-order, a CC register update buffer is prepared as a renaming register for holding update data of the CC register until the commitment.
FIG. 4 is an explanatory diagram of the decoding stage of the CC update instruction in the renaming of the CC register with respect to the previous CC register update instruction of the instruction word register 218-1 and the following CC register read instruction of the instruction word register 218-2 which were simultaneously decoded. A construction of FIG. 4 is fundamentally the same as that in the case of the register update instruction in FIG. 1. That is, by the decoding of the CC update instruction in the instruction word register 218-1, the buffer is allocated onto the register update buffer and information regarding such an allocation buffer is held in a CC renaming map 320. A CC pending bit 322 and an allocation address 324 have been registered in the CC renaming map 320. Simultaneously with the decoding of the CC update instruction in a instruction word register 218, the allocation entry 226-11 corresponding to the instruction is held in the reservation station 226 and an allocation entry 242-11 corresponding to the instruction is also held in the commit stack entry 242. In the allocation entry 226-11 in the reservation station 226, a CC source register area 334 is added subsequently to the first source register area 275. A CC source register area is also added with respect to a second source register area (not shown). A CC pending bit 326, a CC update buffer allocation address 328, a CC bypass ready bit (forward ready bit) 330, and a CC data area 332 are provided in the CC source register area 334. Subsequently, the CC renaming map 320 is referred to by the address of the register serving as a reading source in response to the CC register read instruction of the instruction word register 218-2, the CC pending bit 326 and CC update buffer allocation address 328 in the allocation entry 226-11 of the previous instruction of the reservation station 226 are referred to by the CC pending bit 322 and the allocation address 324, and forward control to the following CC register read instruction is made. In the forward control, the update buffer allocation address obtained from the execution result of the previous CC register update instruction and the CC update buffer allocation address 328 in the allocation entry 226-11 obtained with reference to the CC renaming map 320 by the following register read instruction are compared by a matching process, for example, at a priority stage of the previous instruction. If they coincide, the CC bypass ready bit 330 in the allocation entry 226-11 is set if the CC bypass ready, that is, the forward ready to the following instruction is determined from the execution result of the previous instruction as mentioned above, the instruction executing unit is notified of completion of the preparation on the basis of the CC bypass ready bit 330, the execution result of the previous instruction is forwarded before the commitment, and the following instruction is executed.
In the processor which simultaneously decodes a plurality of instructions, however, in the renaming in the decoding cycle, it is necessary to not only refer to the renaming map in which renaming histories of up to the previous cycle have been registered but also perform the renaming in consideration of the dependent relation with the instruction before the self instruction in the instructions which were simultaneously decoded. In the CC renaming, therefore, only after the complicated instruction decoding processes are executed with respect to both of the CC update instruction and the CC read instruction, the discrimination can be made and the execution of the CC renaming among the instructions which were issued simultaneously becomes a bottleneck in a processor which intends to operate at a high frequency. If the CC source area is provided only for the condition code in which a frequency of instructions is low with respect to the allocation entry of the reservation station, a problem such that resources are increased more than they are needed is also caused.